NEWS: 300mhz "STRETCH" chip beats 2GHZ competition

[roid]

Chip rewires itself on the fly

http://news.com.com/2100-1006-5199930.html

A chip start-up called Stretch is out to revolutionize high-performance hardware.

The Mountain View, Calif.-based company on Monday announced the S5000, which it says is the first processor that can add new instructions while operating. The chip combines an existing RISC (reduced instruction set computing) architecture with a large reconfigurable area of programmable logic called the Instruction Set Extension Fabric, ISEF. The company's own C/C++ compiler automatically spots areas in a program that require intensive computation and creates new instructions for the processor to handle those tasks.

"Operations that might have needed hundreds or thousands of standard instructions can be handled in one," said Gary Banta, chief executive of Stretch. "Designers that have had to use multiple digital signal processor chips or a dedicated programmable logic chip coupled to a general-purpose processor can get equivalent performance with the S5000, just through writing high-level software."

Typical tasks, such as performing encryption or digital video processing on blocks of data, can be executed in single clock cycles.

Banta said the chip has demonstrated 300MHz performance, outperforming 2GHz competition.

...(continues)....

how cool is that?!

[Avder]

So does this mean that theoretically you could builda video card around this thing and catually see it last a few years before becoming obsolete now?

When newer standards come out, just write the instructions to the chip! *makes insane laughing noise thing*

[Tricord]

It depends how you look at it... There isn't a distinct line between hardware and software in terms of microcode... One processor (CISC) can do all instructions in hardware, another processor (RISC) can have a microcode interpreter which splits complex instructions into simpler ones... This microcode interpretation can be done in hardware or in software. In fact, in the beginning days (70s) everything was done in interpreters because hard-wiring an instruction was much more difficult than just assembling microcode in an interpreter.

At univ we wrote our own instructions using microcode. For instance, we had assembler code that repeatedly called ADD and MUL in sequence with the same arguments, so we wrote an instruction in microcode ADML that did the two operations in one cycle.

Also, remember when NVidia launched the GeForce3 series, with the first so-called programmable Nfinite FX engine. It's probably a little trick like this as well where you can tell the individual pieces of the CPU what to do in microcode rather than being limited to a fixed set of instructions.

In this sense the concept of making a CPU that can dynamically add new instructions is as old as dirt, only it hasn't been done in hardware before... Pretty nice!

[rijruna]

I can seem to remember a couple of posts here about the limits of silicone based chips in the not-too-distant past. maybe these ppl have gone & solved that question for us. coupled with the set-up the ppl whom roid poseted about should mean some wickedly fsat, tiny D3 playing machines for next to zero compared to todays prices hhhhmmmmm yum.
cheers
rij

http://news.com.com/2008-1082_3-963098.html?tag=st_rn

[roid]

from the article it seemed like the chip actually rewrites large parts of itself on the fly, depending on what kinds of computations it predicts it needs to do a lot of in the upcomming code. it doesn't need to stop and reflash/reprogram itself, it constantly looks ahead in the code (this look-ahead process in itself is nothing new) and changes as it goes.

so theoretically as the pc is pulling video data from the HDD, the chip is buzy rewriting itself to be superfast at video computations.

a better example would be a chip that seems to be designed specifically to play whatever game you are CURRENTLY playing.
you wanna play D3? congrats, your chip was designed for that. Quake 5? well what dya know, the chip now has Quake 5 code wired directly into it.

with a technique like that it's no wonder it blows the other higher MHZ (uh, i mean GHZ) chips away.

also, i just noticed that these higher mhz chips it's being compared to, they seem to all be high performance number crunching chips. i mean, i don't recognize any of the names of those chips, they must be supercomputer chips or something.
ie: these 2GHZ chips that it overperformed were not exactly AMD or INTEL desktop chips, they were much more.
see: http://www.stretchinc.com/products_benchmarks.php

[Mr. Perfect]

So does this mean that theoretically you could builda video card around this thing and catually see it last a few years before becoming obsolete now?

When newer standards come out, just write the instructions to the chip! *makes insane laughing noise thing*

Yeah, like Nvidia and ATI are gonna make something you can use for the next 3 years...

[Top Wop]

I'd like to see the real thing in action. When do computers with this chip and mobo go out into the market? The saying "If its too good to be true..." kicks in.

[Tricord]

from the article it seemed like the chip actually rewrites large parts of itself on the fly, depending on what kinds of computations it predicts it needs to do a lot of in the upcomming code. it doesn't need to stop and reflash/reprogram itself, it constantly looks ahead in the code (this look-ahead process in itself is nothing new) and changes as it goes.

so theoretically as the pc is pulling video data from the HDD, the chip is buzy rewriting itself to be superfast at video computations.

a better example would be a chip that seems to be designed specifically to play whatever game you are CURRENTLY playing.
you wanna play D3? congrats, your chip was designed for that. Quake 5? well what dya know, the chip now has Quake 5 code wired directly into it.

Sounds like dynamic interpreting to me. If you know anything about the hardware structure of a CPU (ALU, control unit, registers, pipeline, memory interface) you know you can't create something that is foggy and just wires itself according to executed code. There is probably still a main ALU that works the same as any other ALU, but a co-processor that can dynamically interpret assembler code, identify repetitive tasks and recombine multiple instructions into one in microcode... Sounds like a nightmare to pull off, but would certainly be beneficial in repetitive tasks (loops, and by extent games, encoders, etc..).

On the other hand, every optimisation introduces a tradeoff someplace else. For instance, an instruction pipeline may block on an instruction waiting for the memory to kick in, causing a pipeline flush and refetch of all previously pipelined instructions. So, you might want to re-optimize your assembler code by inserting NOP instructions, so that if an instruction waits for memory the pipeline doesn't block and flush.

In this case I don't think this CPU architecture will give a golden solution to all problems. It is still specifically tailored to dynamic microcoding, so there will be plenty of situations where it performs actually a lot slower than a conventional CPU.

Another thought, which is more interesting, is that if you have a machine with such a CPU, it can run MAC, SPARQ, intel32, intel64, MC, etc.. code without need for other hardware... So, dual booting Solaris and WinXP would be possible

[Diedel]

From what the quoted text in the first post says it looks like some of you are mistaking the workings of that processor a little.

It's the compiler that determines at compile time which instructions can be made into low level micro ops for that chip and be stored in it's dynamic instruction cache.

I also doubt that an extremely complicated operation can be executed in 1 clock cycle. Current CPUs contain a lot of instructions that perform already pretty complicated stuff, and these instructions take several clock cycles to execute - and they are 'hand coded', so should be pretty efficient.

The concept is interesting, but the talk above is rather about "marchitecture" than architecture, imho.